Sample Exam Paper 2 (without solutions)
A regular, cyclic signal performs a complete excursion (0 to 1) during the time it takes the signal to propagate five inches along a PCB track. If signals propagate at 70% c along the PCB, what is the clock frequency?
What determines the maximum clock frequency in a computer?
What, if anything, determines the minimum clock frequency?
Suppose a new generation of RISC-
What are the practical hurdles and barriers that the designer of an ISA with 4-
Why is the multiply and add instruction the best thing since sliced bread?
Why do so many processors support such a large number of different shift instructions?
How many different shift instructions (or variations on a shift instruction) are there?
How many shift instructions do we really need in a minimal instruction set?
The 68020 microprocessor supported an addressing mode of the form ([A0],A1). This addressing mode uses pointer register A0 to read a location in memory. The contents of address register A1 is added to the value obtained from memory to create the effective address of the operand. What is the advantage of such an addressing mode? What are its disadvantages?
Why does Amdahl’s law give a rosy (optimistic) view of parallel processing?
Why does Amdahl’s law give a pessimistic view of parallel processing by indicating barriers (limitations) that don’t exist?
Suppose that I indicates the instruction count of a program, C indicates the average number of clock cycles per instruction, and T indicates the clock cycle time, the total time required to execute a program is I.C.T.
a. How can we reduce the product I.C.T?
b. Whose job is it (the programmer, the microarchitect, the chip designer, the device physicist)?
c. To what extent are the terms I, C, and T interrelated and to what extent are the independent?
d. Does I.C.T provide a realistic model for the benchmark of a computer? If not, why not?
You wish to speed up an ARM-
a. Write two ARM code fragments to move a block for Count words from Source to Destination using conventional code and then using MBLK.
b. If you implement the MBLK instruction using dedicated hardware, what new logic blocks and data paths need be added to a conventional pipelined computer?
c. What speedup does the MBLK provide (for the block move operation)?
d. Can you think of a way of increasing the speed of the MBLK instruction?
Compare and contrast the branching philosophies of the ARM and MIPS processors. This question is asking about the ISA and not branch implementations technologies such as branch prediction.
Some microprocessors have many branch conditions (typically, up to 16). Some have very few branch conditions. Why? And why are 16 branch conditions sometimes provided?
Consider the flowing fragment of ARM-
Loop LDR r0,[r1]
a. Highlight all true data dependencies in this code.
b. Assume that there is no data forwarding. Provide an instruction sequence diagram for the first two loop transits.
c. Repeat the exercise using data forwarding.
RAID 0 seems pointless. It doesn’t provide any level of the data redundancy required to improve reliability. Instead it uses a technique called striping to improve disk performance. What exactly is striping and how does it improve I/O performance? Why might a person prefer to have 2 (or more) independent drives rather than have them in a RAID 0 setup?
a. What does RAID 0 offer the user and why would anyone use it?
b. Why would someone decide not to use RAID 0 and instead opt for two separate independent drives?
RAID 1 provides redundancy and reliability via mirroring disks. Why bother? Why not just use two separate drives and backup data yourself.
What are the differences between RAID 3 and RAID 4 systems and why are they rarely used today?
What form of RAID system is often used in the commercial world of large-
The ARM processor provides predicated execution where an instruction is not executed
unless a specific condition is set. In the case of the ARM, the condition is one
of the normal 16 branch conditions specified by the condition code register; for
example ADDEQ r0,r1,r2 will add r1 to r2 and out the result in r0 if and only if
the Z flag is set; that is, if the result of the last operation to update the Z-
23. Suppose the ARM’s ISA is redesigned to support a more sophisticated form of predicated
instruction. The new instruction format is Pi_Op, where Pi is a one-
a. What is the advantage of having two complementary predicate registers?
b. What is the advantage of this arrangement over the existing ARM predication mechanism?
Consider the following fragment of ARM code.
Mult1 MUL r8,r9,r10
c. Rewrite this code using ARM’s predicated instruction set. What do you gain by using predicated execution? What, if anything, do you lose by using predicated execution?
Consider the following code fragment.
NoClr STR r4,[r7]
Mult1 MUL r8,r9,r10
d. Translate this into conventional ARM code using predicated execution.
e. Rewrite this code using operations of the form CMPcc ra,rb,PiT,PjF that we suggested above.
f. What are the advantages of this form of predication (over the ARM’s predication based on the status flags in the condition code register)?