The No Operation Instruction
A NOP or no operation is an instruction that isn’t. It’s something that no one ever thinks about. People think less about NOPs than about where all those biros go when they die. And yet.
A no operation instruction is an instruction that performs no operation. This, itself, is a paradox rather like Russell’s barber paradox (If the barber shaves all those men who do not shave themselves, who shaves the barber?). So, what are NOPs and why are they used?
A NOP is a computer instruction that does nothing apart from advance the program
counter. It’s a waste of time and of the space it occupies in memory. The standard
definition of a NOP is that is should serve only to advance the program counter by
one instruction ([PC] ¬ [PC] + 4 in a 32-
When I first became interested in microprocessors in the late 1970s it was the era
of the 8-
To help limit the effect of errors, programmers would often place a string of NOPs at strategic points in code. If they later found an error, they could either patch the code by replacing the NOPs or they could replace NOPs by a jump to a suitable memory location where the fix could be made. Today, you’d correct and error and recompile the code; something that was not always possible in those days. Few engineers admitted even using this technique and I was once admonished for even suggesting it. NOPs could also be used to introduce delays in code for timing purposes because if a NOP takes n microseconds, then m NOPs take m·n microseconds.
The Motorola 6800 8-
When the RISC pipelined processor became popular, NOPs could be used to introduce delays when necessary; for example, following a load operation. I once heard of the use of NOPs to solve a problem that cause anomalous behaviour of the processor when a certain sequence of instructions was executed. Inserting a NOP cured this fault. The principal uses of a NOP are:
To allow the future modification of code without rewriting or recompiling it
To add a known delay
To deal with hazards and sequencing problems in pipelines
To enforce the order of execution of sequences of instructions (to prevent out-
To align code/data on an appropriate boundary
To synchronize events
Not all NOPs are equal, and it was this thought that drove me to write this note.
The MIPS RISC has a NOP. However, on closer examination, the NOPs is really a pseudo-
When you write NOP in MIPS code it is translated to ssl $r0,$r0,0 which means shift
register r0 left zero places and put the result in $r0. Since $r0 is hardwired to
zero, this instruction has no effect and can be treated as a no operation. Moreover,
since the numeric value for this is 0x00000000 (all zeros) it means that non-
ARM code can use ANDEQ r0,r0,r0 which has an all zeros op-
I feel that a true NOP should have a unique op-
The most intriguing NOP I ever encountered was the Itanium NOP, for two reasons.
First, the Itanium is a VLIW processor and bundles of instructions are executed in
parallel. The instructions of a bungle to be executed are selected by the programmer
or assembler/compiler. In Itanium assembly language a suffix can be assigned to
an operation to define which of the parallel using is going to handle it (e.g., memory,
An even more fascinating concept arises in the case of predicated processors like the ARM and Itanium. Consider the ARM predicated form of the no operation and NOPNE. When this instruction is decoded and sent for execution, the predication marker, NE, signifies not zero. So, if the previous condition code was zero, the predicated instruction is not executed. If the previous condition code was not zero, the NOP is executed ad nothing happens.
Finally, what is the perfect NOP? Apart from having its intended effect (incrementing
the PC) and leaving the processor status unmodified, it should have a unique op-