The 68K Family
I was in the right place at the right time. In the late 1970s I was a postgraduate working on digital data transmission and considering the use of microprocessors, rather than dedicated logic, at the time microprocessors were becoming available. For various reasons, I became involved with the Motorola 68000 family.
The 68000 family, or 68K, was one of the first so-
The 68K initially enjoyed considerable success. It was chosen for Sun workstations, the Apple Macintosh, the Amiga, and the Atari computers. Sega adopted the 68K for its Mega Drive Console. Like other companies, Motorola produced new versions of the 68K family with ISA enhancements and greater speed. However, the 68K did not thrive. IBM’s PC based on Intel’s IA32 architecture became dominant. Even Apple eventually adopted the IA32 architecture. The 68K lives on today as a microcontroller family marketed by Freescale Semiconductor.
Why the 68K?
The 68K became very popular in the world of computer architecture education and,
for many, it was the preferred means of introducing the ISA to students. The reason
for this is simple. The 68K architecture is very easy to teach and it’s very easy
to understand. It’s architecture is regular (but not perfectly so) and it has some
very interesting attributes such as prioritized, vectored interrupt-
Moreover, Motorola created a large amount of teaching material for the 68K and several simulators were freely available in the public domain, which made the 68K an ideal vehicle for class use.
However, because the 68K has dropped out of fashion today, it is no longer feasible
to use it as a teaching vehicle in many architecture/organization courses today.
I have included this section on the 68K because it is interesting; it played a significant
role in the history of computing; it is easy to understand, and because it probably
represents the high-
The 68K Simulator
An important reason for including this section is that an excellent 68K assembly
and simulator for teaching use is available. The software is called EASy68K and was
developed and maintained by Professor Charles Kelly at the Monroe County Community
College in Michigan. There is a web site devoted to EASy68K which is distributed
under the GNU public use licence. You can download the editor and simulator as a
EASy68K is easy to use. You first edit a 68K program and then run it in simulation mode. Like the ARM and MIPS simulators, you can step through a program instruction by instruction and observe the way in which registers and memory change as a program is executed.
Introduction to the 68K ISA
The 68K has 16 32-
Differences Between Address and Data Registers
A data register can take part in 8-
Operations on data register automatically update condition code bits (unlike the ARM, no special update suffix is necessary).
Address registers are pointers and can only take part in addition, subtraction, and
comparison operations. Moreover, operations on address registers do not affect condition
codes (apart from compare). You can apply only 32-
The 68K has a classic CISC multilength format; that is an instruction can be as short
as two bytes (16 bits) or 10 bytes (80 bits). Instructions can have zero, one, two,
or three operands. The 68K ISA supports register-
The 68K is one of the few processors that supports an operation like MOVE.B P,Q which
copies the contents of memory location P to memory location Q. Addresses P and Q
can be full 32-
Equally, you can write MOVE.B (A1),(A2) that moves the contents of the memory pointed
at by A1 into the location pointed at by A2. Finally, you can write MOVE.L #$12345678,P
which moves the 32-
Typical data processing operations are:
As you can see, typical arithmetic and logical operations are supported and that the source may be a literal, register or memory location, and the destination a register or memory location.
Simple 68K Program
Let’s look at a simple 68K program that reads two values from memory, adds them and stores the result. The following fragment of code conforms to typical 68K conventions in program layout and the use of 68K assembler directives. It is not that dissimilar to an ARM program.
ORG $400 ;Start of program area
MOVE.B Value1,D0 ;Load D0 from memory
ADD.B D0,D1 ;Add D0 to D1
MOVE.B D1,Result ;Store the sum in memory
STOP #$2700 ;Stop execution
ORG $1000 ;Start of data area
Value1 DC.B 12 ;Store “12” in memory
Value2 DC.B 24
Result DS.B 1 ;Reserve a byte for “Result”
END $400 ;End of program and entry point
The ORG (origin) is an assembler directive that defines the point at which the following instructions and data are to be loaded in memory. In this case the program starts at 0x400 (by convention because memory space from 0x0000 to 0x3FF is used to store exception vectors). The second ORG statement indicates that data is to be loaded in memory from location 0x1000 onward.
As in the case of ARM, anything beginning in the first column is a lable. In this case, Value1 is a label for address location 0x1000 where the value 12 is stored as one byte (the assembler directive DC.B reserves one byte and gives it the value 12). Similarly Value2 DC.B 24 stores the value 24 in memory location 0x1001. Finally, Result DS.B 1 reserves 1 byte at location 0x1002 and this location is called “Result”.
The 68K can use absolute or direct addresses. Hence, MOVE.B Value1,D0 means copy
the contents of memory location Value1 into the low-
The MOVE.B D1,Result instruction copies the result in D1 to memory location Result.
The 68K has an explicit halt instruction called STOP that usually takes the parameter $2700 (this parameter is loaded into the processor status word).
Recall that the ARM does not have explicit shift instructions; the second operand is fed through a barrel shifter and can be shifted on its way to the ALU. A typical operation is ADD r0,r1,r3, LSL #4. Where the contents of register r3 are shifted left four times and then added to register r1 and the result deposited in register r0. You can also express the number of shifts dynamically, making this a four register operation.
The 68K provides a comprehensive set of shift operations; logical, arithmetic, rotate (circular), and rotate through the extend bit (the extend bit is a copy of the carry bit). Typical shift operations are:
LSL.B #4,D0 ;shift the contents of the lower order byte of D0 left logically by 4 places
LSR.W #8,D1 ;shift the contents of the lower order 16 bits of D1 right logically by 8 places
ASL.B #1,D2 ;shift the contents of the lower order byte of D2 left arithmetically by 1 place
ASR.L #7,D0 ;shift the contents of D0 right arithmetically by 7 places
ROL.L #6,D4 ;rotate the contents of D4 left by 6 places
ROR.B D2,D0 ;rotate the contents of the lower order byte of D0 right by the value in D2
ROXL.W #4,D6 ;rotate the contents of D6 left through eXtend left logically by 4 places
ROXR.L D3,D1 ;rotate the contents of D1 right through eXtend by the value in D3
LSL.W P ;shift the contents of the word at location P logically left by one place
These examples demonstrate:
1. You can use .B, .W, or .L extensions.
2. You can shift by a fixed number of places ( 1 to 8) or by a variable number of places.
3. You can apply a shift directly to a memory location. However, the shift must be one place.
Bit Manipulation Instructions
The 68K allows you to operate on the bits of a register. You can test the value of a bit, set it, clear it, or toggle it. Consider the following:
BTST #4,D0 ;test the value of bit 4 of D0. If zero, set the Z-
BTST D1,D0 ;test the value of the bit of D0 whose position is specified by
D1. If zero, set the Z-
BSET #21,D3 ;set the value of bit 21 of D3 to 1
BCLR D2,D7 ;clear the value of the bit of D7 whose position is specified by D2 to 0
BCHG #8,D3 ;toggle the value of bit 8 of D3 (i.e., set it to its complement)
BCHG #2,P ;toggle the value of bit 2 of memory location P
These operations can be applied to the entire contents of a data register (the .L extension is not needed). The operations can also be applied to the 8 bit contents of a memory location. You can perform all these actions in an ARM environment by using standard logical operations.
Addressing Modes (Link)
Addressing modes are concerned with the way in which we specify the location of an operand. In 68K literature you write an operation like CLR <ea> to indicate the instruction clear that sets the contents of the effective address to zero. The notation <ea> indicates effective address and stands for any legal address mode that this instruction may use. The 68K has rather more addressing modes than RISC processors like the ARM or MIPS. Follow this link for more details on addressing modes.
The 68K family has an interesting feature; it’s twin operating modes called user and supervisor. For a short article on this aspect of the 68K follow this link.