The PowerPC is an interesting processor, both because of its architecture and because of its history or pedigree.
The origins of the PowerPC can be traced back to the IBM 801 project led by John
Cocke in the mid-
Motorola had created its own RISC architecture, the 88000 but that family did not do well in the market place. Motorola hoped that by scrapping the 88000 and jumping into bed with IBM (remember the saying “No one ever got fired for buying IMB”) and Apple, success was guaranteed. Initially, it looked as if the PowerPC would be a success for Motorola and IBM as Apple’s computers adopted PowerPCs.
Motorola’s line of PowerPC processors, G1, G2, G3, G4, G5, never achieved the expected
level of success for several reasons. The WinTel alliance was very strong and potential
adopters were put of using the PowerPC architecture. Motorola has difficulties in
manufacturing the more advanced processors and eventually sold off its semiconductor
arm to Freescale. Apple persisted with PowerPC-
The POWER architecture lives on in the IBM world where the Power 760 is a high-
It’s RISC Jim, but not as we know it
The PowerPC has a 32-
Probably the first question you ask about an ISA is “What registers does it have?”
The PowerPC is a register-
The 32 general-
At first sight, this looks like any other register. Look again and you can see that
The following figure describes the PowerPC’s user visible register set.
The 32 general-
We do not delve deeply into the PowerPC’s user visible control and status registers. These are:
CR (Condition register) The condition register is a 32-
LR (Link register) The link register performs a similar function that in the ARM
or MIPS. It holds a rerun address. The link register is 32 bits in 32-
XER (Integer Exception Register) The integer exception register is really an extension of the traditional condition flag register. It contains two overflow bits. SO is a summary overflow bit that is set whenever an instruction sets the overflow bit, OV, and it remains set until cleared by software. That is, SO is a sticky overflow bits that says “overflow has occurred on my watch”. The OV, overflow bit, is a conventional overflow bit that is set by the generation of an overflow.
CA (Carry) The carry bit is set to indicate that a carry out occurred during the execution of an instruction.
Byte count The byte count field of the XER register is used to hold the byte count requires by special loaf string word and store string word instructions.
CTR (Count register) The count register is a 32-
TBL/TBU (Time base registers) The time base registers provide a real-
Power PC Addressing Modes
I was brought up on the 68K and later the 68020. As you can imagine I thought that any addressing mode more primitive than ([100,A3,D2.W],64) was embarrassingly crude. I believed that it was not what you did with data that mattered but how cleverly you could express its location no matter how deeply it was buried in a data structure.
When I first encountered RISC processors, I was astounded that they provided only a single simple register indirect addressing format expresses in the form like 4(A3) or [r2,#6]. So, why had the gods given us complex addressing modes in the first place? My colleagues explained that the gift of complex addressing modes was a temporary loan until we’re developed optimizing compilers that could make far better use of primitive addressing modes.
Both MIPS and ARM have a simple register plus offset addressing mode, although ARM
does allow pre-
The powerPC has gently extended addressing modes to provide double indexing.
The simplest addressing mode is register with offset; for example, the PowerPC instruction lwz r3,12(r5) is the same as the ARM equivalent LDR r3,[r5,#12].
The PowerPC’s indexed modes allows the use of two registers and we can write lbzx r1,(r3,4),r5. The mnemonic indicates load unsigned byte with index. Here, the index register is r5 and that is used to create the effective address [r3] + 4 + [r5]. WE can also used indexed addressing with update in which the index is permanently added to pointer register. Updating is indicated by appending a u to the mnemonic to get lbzxu rather than by adding a ! To the effective address a la ARM.
TO BE EXTENDED